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PI6C100
Precision Clock Synthesizer for Desktop PCs
Features
Four copies of CPU clock with VDD of 2.5V + 5% 100 MHz or 66 MHz operation Eight copies of PCI clock, (synchronous with CPU clock) 3.3V Two copies of IO APIC clock @14.31818 MHz Two copies of 48 MHz clock Three copies of Ref. clock @14.31818 MHz (3.3V TTL) Low cost 14.31818 MHz crystal oscillator input Spread spectrum modulation of CPU and PCI clocks for reduced EMI Power management control Isolated core VDD, VSS pins for noise reduction 48-pin SSOP package (V48)
Description
The PI6C100 is a high-speed low-noise clock generator designed to work with the PI6C180 clock buffer to meet all clock needs for Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWRDWN# signal may be used to orderly power down (or up) the system.
Block Diagram
Pin Configuration
*KBBAHI
VDDREF XTAL_IN XTAL_OUT REF OSC 3 REF[0:2] VDDAPIC VDDCPU 0,1 4 CPUCLK[0:3] PLL1 /2 CPUSTOP# VDDPCI 0,1 7 PCICLK[1:7] PCISTOP# PCICLK_F VDD48MHz PLL2 2 48MHz 2 APIC0,1
SEL0,1 SPREAD# SEL100/66#
VSSREF XTAL_IN XTAL_OUT VSSPCI0 PCICLK_F PCICLK1 VDDPCI0 PCICLK2 PCICLK3 VSSPCI1 PCICLK4 PCICLK5 VDDPCI1 PCICLK6 PCICLK7 VSSPCI2 VDDCORE0 VSSCORE0 VDD48MHz 48MHz 48MHz VSS48MHz
REF0 REF1
48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 9 48-Pin 40 10 V48 39 38 11 37 12 36 13 35 14 34 15 33 16 17 32 18 31 19 30 20 29 21 28 22 27 23 26 25 24
VDDREF REF2 VDDAPIC APIC0 APIC1 VSSAPIC NC VDDCPU0 CPUCLK0 CPUCLK1 VSSCPU0 VDDCPU1 CPUCLK2 CPUCLK3 VSSCPU1 VDDCORE1 VSSCORE1 PCISTOP# CPUSTOP# PWRDWN# SPREAD# SEL0 SEL1 SEL100/66#
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PI6C100 Precision Clock Synthesizer for Desktop PCs
Pin Description
Pin 1,2,47 3 48 4 5 6,12,18 7 9,15 8,10,11,13, 14,16,17 19,33 20,32 21 24 22,23 26,27 25 29 30 31 37,41 34,38 35,36,39,40 43 46 44,45 28 42 Signal Name REF[0:2] VSSREF VDDREF XTAL_IN XTAL_OUT VSSPCI[0:2] PCICLK_F VDDPCI[0:1] PCICLK[1:7] VDDCORE[0:1] VSSCORE[0:1] VDD48MHz VSS48MHz 48MHz SEL[0:1] SEL100/66# PWRDWN# CPUSTOP# PCI_STOP# VDDCPU[0:1] VSSPCU[0:] CPUCLK[0:3] VSSAPIC VDDAPIC APIC[0:1] SPREAD# NC Type O ground power I O ground O power O power ground power ground O 1 I I I I power ground O ground power O I 1 2 2 4 1 1 2 1 1 Qty. 3 1 1 1 1 3 1 2 7 2 2 1 1 2 2 1 1 De s cription 14.318 MHz clock output. Ground for REF[0:2] outputs Power for REF[0:2] outputs 14.318 MHz crystal input. 14.318 MHz crystal output. Ground for PCI clock outputs Free running PCI clock output Power for PCI clock outputs PCI clock outputs, TTL compatible 3.3V Isolated power for core Isolated ground for core Isolated power for 48 MHz outputs Isolated ground for 48 MHz outputs 48 MHz outputs Logic select pins. LVTTL levels Select pin for enabling 100 MHz or 66 MHz H = 100 MHz. L = 66 MHz Powers down device when held LOW Stops CPU clocks LOW if held LOW Stops PCI clocks LOW if held LO W Power for CPU outputs Ground for CPU outputs CPU and Host clock outputs 2.5V Ground for APIC outputs Power for APIC outputs APIC outputs @2.5V. 14.31818 MHz Enables Spread Spectrum feature when LO W Reserved for future modification
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PI6C100 Precision Clock Synthesizer for Desktop PCs
Select Functions
SEL100/66# 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 Function Hi- Z Reserved Reserved 66 MHz active Test mode Reserved Reserved 100 MHz active
Function D e s cription Hi- Z Test Mode
Outputs CPU Hi- Z TCLK /2 PCI, PCI F Hi- Z TCLK /6 48M Hz Hi- Z TCLK /2 REF[0:2] Hi- Z TCLK IOAPIC Hi- Z TCLK
Note: TCLK is a test clock over driven on the XTAL_IN input during test mode.
Clock Enable Configuration
CPU_STOP# X 0 0 1 1 PCI_STOP# X 0 1 0 1 PWR_D WN# 0 1 1 1 1 CPUCLK low low low 100/66 MHz 100/66 MHz PCICLK low low 33 MHz low 33 MHz Othe r Clocks Stopped running running running running Crys tal off running running running running VCO's off running running running running
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PI6C100 Precision Clock Synthesizer for Desktop PCs
CPU_STOP# is an input signal used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock and is internally synchronized to the external PCICLK_F output.
All other clocks continue to run while the CPU clocks are disabled. The CPU clocks are always stopped in a low state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or 3 CPU clocks.
Power Management Timing
Signal CPU_STOP# Signal State 0 (disabled) 1 (enabled) PCI_STOP# 0 (disabled) 1 (enabled) PWR_DWN# 1 (normal operation) 0 (power down Late ncy No. of ris ing e dge s of fre e running PCICLK 1 1 1 1 3ms 2 max.
Notes: 1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between when the clock disable goes low/high to when the first valid clock comes out of the device. 2. Power up latency is from when PWR_DWN# goes inactive (high) to when the first valid clocks are driven from the device.
CPUCLK (Internal) CPUCLK (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK (External)
CPU_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3 CPU_STOP# is an input signal that is made synchronous to the free running PCICLK_F. 4. ON/OFF latency shown is 2 CPU clocks.
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PI6C100 Precision Clock Synthesizer for Desktop PCs
PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.
CPUCLK (Internal) PCICLK (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PWR_DWN# PCICLK (External)
PCI_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only.
The PWR_DWN# is used to place the device in a very low power state. PWR_DWN# is an asynchronous active low input. Internal clocks are stopped after the device is put in power down mode. The power on latency is less than 3ms. PCI_STOP# and CPU_STOP# are dont cares during the power down operations. The REF0 clock is stopped in the LOW state as soon as possible.
CPUCLK (Internal) PCICLK (Internal) PWR_DWN# CPUCLK (External) PCICLK (External) VCO Crystal
PWR_DWN# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
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PI6C100 Precision Clock Synthesizer for Desktop PCs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................................................65C to +150C Ambient Temperature with Power Applied .................................... 0C to +70C 3.3V Supply Voltage to Ground Potential ....................................... 0.5V to +4.6V 2.5V Supply Voltage to Ground Potential ....................................... 0.5V to +3.6V DC Input Voltage ............................................................................ 0.5V to +4.6V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (VDDQ3 = +3.3V 5%, VDDQ2 = +2.5V 5%, TA = 0C to +70C)
Parame te rs IIL VIL VIH VOL VOH IDDQ2 IDDQ2 IDDQ2 IDDQ3 IDDQ3 IDDQ3 CIN COUT LPIN TA Input Capacitance O utput Capacitance Pin Conductance Ambient Temperature No Airflow 0 3.3V Supply Current 2.5V Supply Current D e s cription Te s t Conditions M in. -5 VSS - 0.3 @VDD IOL = 1mA, VDD = Min. IOL = - 1mA, VDD = Min. VDDQ2 = 2.625V, PWRDWN#=0 CLOAD = Max. VDDQ2 =2.625V @ 66.66 MHz CLOAD = Max. VDDQ2 =2.625V @ 100 MHz CLOAD = Max. VDDQ3 =3.465V, PWRDWN#=0 CLOAD = Max. VDDQ3 =3.465V, 66.66 MHz CLOAD = Max. VDDQ3 =3.465V, 100 MHz CLOAD = Max. 2 100 72 mA 100 500 170 mA 170 5 6 7 70 pF nH C A A +2.0 Typ. M ax. +5 0.8 VDD +0.3 0.4 V Units A Input Leakage Current 0V < VIN < VDD Input Low Voltage Input High Voltage O utput Low Voltage O utput High Voltage
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PI6C100 Precision Clock Synthesizer for Desktop PCs
DC Operating Specifications
Symbol Parame te rs Conditions M in. M ax. Units Input Voltage , VDDCORE [0-1] = 3.3V 5% VIH3 VIL3 IIL VOH2 VOL2 VOH3 VOL3 VPOH VPOL CIN CXTAL COUT LPIN TA Input high voltage Input low voltage Input leakage current 0 < VIN < VDDCORE IOH = - 1mA IOL = 1mA IOH = - 1mA IOL = 1mA IOH = - 1mA IOL = 1mA 2.4 0.55 2.4 0.4 VDDCORE 2.0 VSS - 0.3 -5 VDDCORE +0.3 0.8 +5 V A
Output Voltage = 2.5V 5% VDDAPIC, VDDCPU [0-1] O utput high voltage O utput low voltage 2.0 0.4 V
Output Voltage = 3.3V 5% VDDREF O utput high voltage O utput low voltage V
Output Voltage = 3.3V 5% VDDCPI [0-1] PCI Bus output high voltage PCI Bus output low voltage V
Input pin capacitance XTAL pins capacitance O utput pin capacitance Pin Inductance Ambient Temperature No airflow 0 13.5 18.0
5 22.5 6 7 70 nH C pF
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PI6C100 Precision Clock Synthesizer for Desktop PCs
Buffer Specifications
Buffe r Name CPU APIC 48MHz, REF PCI
VDD Range (V) 2.375 - 2.625 2.375 - 2.625 3.135 - 3.465 3.135 - 3.465
Impe dance ( ) 13.5 - 45 9 - 30 20 - 60 12 - 55
Buffe r Type Type 1 Type 2 Type 3 Type 4
Type 1: CPU Clock Buffers (2.5V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 1 1 27 30 4 4 V/ns M in. - 27 - 27 mA Typ. M ax. Units
2.5V Type 1 output rise edge rate 2.5V + /- 5% @ 0.4V- 2.0V 2.5V Type 1 output fall edge rate 2.5V + /- 5% @ 2.0V- 0.4V
Type 2: APIC Buffers (2.5V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 2.5V Type 2 output rise edge rate 2.5V Type 2 output fall edge rate Conditions VOUT = 1.4V VOUT = 2.5V VOUT = 1.0V VOUT = 0.2V 2.5V 5% @0.4V- 2.0V 2.5V 5% @2.0V- 0.4V 1 1 36 31 4 V/ns 4 M in. - 36 - 21 mA Typ. M ax. Units
Type 3: 48MHz, REF Buffers (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 3 output rise edge rate 3.3V Type 3 output fall edge rate Conditions VOUT = 1.0V VOUT = 3.135V VOUT = 1.95V VOUT = 0.4V 3.3V 5% @0.4V- 2.4V 3.3V 5% @2.4V- 0.4V
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M in. - 29
Typ.
M ax.
Units
- 23 29 27 0.5 0.5 2
mA
V/ns 2
PS8142A 10/13/98
AC Timing
Figure 1. Hos t Clock to PCI CLK Offs e t tHKP (2.5V) tHKH (2.5V) tHKL (2.5V) tHRISE (2.5V) tHFALL (2.5V) tJITTER (2.5V) Duty Cycle (2.5V) tHSKW (2.5V) tIOSKW tPZL, tPZH tPLZ, tPHZ tHSTB tPKP tPKPS tPKH tPKL tPSKW tHPOFFSET tPSTB Parame te rs Host CLK period Host CLK high time Host CLK low time Host CLK rise time Host CLK fall time Host CLK Jitter Measured at 1.25V Host Bus CLK Skew IO APIC Bus CLK Skew Output enable delay Output disable delay Host CLK Stabilization from power- up PCI CLK period PCI CLK period stability PCI CLK high time PCI CLK low time PCI Bus CLK Skew Host to PCI Clock Offset PCI CLK Stabilization from power- up 1.5 12.0 12.0 500 4.0 3 1.5 30.0 1.0 1.0 45 66 M Hz M in. 15.0 5.2 5.0 0.4 0.4 1.6 1.6 250 55 175 250 8.0 8.0 3 500 12.0 12.0 500 4.0 3 30.0 1.0 1.0 45 M ax. 15.5 100 M Hz M in. 10.0 3.0 2.8 0.4 0.4 1.6 1.6 250 55 175 250 8.0 8.0 3 500 ps % ps ns M ax. 10.5 Units
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PI6C100 Precision Clock Synthesizer for Desktop PCs
Type 4: PCI Clock Buffers (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 4 output rise edge rate 3.3V Type 4 output fall edge rate Conditions VOUT = 1.0V VOUT = 3.135V VOUT = 1.95V VOUT = 0.4V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 1 1 30 38 4 V/ns 4 M in. - 33 - 33 mA Typ. M ax. Units
ns ms ns ps ns ps ns ms
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2.5V 1.25V Host CLK t HSKW 2.5V 1.25V Host CLK t HPOFFSET 1.25V V t HPOFFSET 3.3V 1.5V PCI CLK t PSKW 3.3V 1.5V PCI CLK V 1.5V V 1.25V V SS SS SS SS
PI6C100 Precision Clock Synthesizer for Desktop PCs
Figure 1. Host Clock to PCI CLK Offset
Output Buffer Test Point
Test Load
tHKP Duty Cycle
tHKH 2.0 0.4
2.5V Interface
Clocking 1.25
tHKL tHrise tHfall
tPKP
tPKH 3.3V Clocking Interface (TTL) 2.4 1.5 0.4
tPKL tPrise tPfall
Figure 2. Clock Output Waveforms
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PI6C100 Precision Clock Synthesizer for Desktop PCs
Minimum and Maximum Expected Capacitive Loads
Clock CPU Clocks (HCLK ) PCI Clocks (PCLK ) 48 MHz Clock REF APIC M in. Load 10 30 10 10 10 M ax. Load 20 30 20 20 20 pF Units Note s 1 device load, possible 2 loads Meets PCI 2.1 requirements 1 device load 1 device load 2 device loads
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500W resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
21$+
CPUCLK 4 33 1 Device load CL 8 33 Meets PCI2.1 Req. CL 3 22/33 1 Device load CL 2 33 2 Device loads CL 2 22 1 Device load CL
PCICLK
REF
APIC
48MHZ
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PI6C100 Precision Clock Synthesizer for Desktop PCs
PCB Layout Suggestion
C11 FB1 C2 VCC VSS 1 2 3 4 C1 VSS 22uF 7 C3 VDD 8 9 10 11 VSS 12 13 C4 VDD 14 15 16 17 C5 VSS 18 19 20 21 22 23 VSS 24 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Via to VDD Plane 27 26 25 Via to GND Plane VSS C7 VSS C8 22uF C9 VDD 5 6 48 47 46 45 44 43 VSS C12 VDD
C10 VDD FB2 VCC (CPU)
VDD
VDD VSS
VDD C6 VSS
VDD
Void in Power Plane
Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C2-C11 should be placed as close as possible to their respective VDD.
Recommended capacitor values: C2-C11 .............. 0.1F, ceramic C1, C12 ........... 22F
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PI6C100 Precision Clock Synthesizer for Desktop PCs
48-Pin SSOP Package Data
48
.395 .291 .420 .299 7.39 10.03 7.59 10.67
Gauge Plane .010 0.25 .02 .04 0.51 1.01
1 .620 .630 15.75 16.00 .008 0.20 Nom.
.015 0.381 x 45 .025 0.635
.110 2.79 Max 0-8 .008 0.20 .016 0.40 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.025 BSC 0.635
.008 .0135 0.20 0.34 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Table of Dimensions
Body 48 pins (300 mil) Min. Max. E (Width) 0.291 0.299 D (Le ngth) 0.620 0.630 A (He ight) 0.095 0.110 e (Pin-to-Pin pitch) 0.025 -
Ordering Information
P/N PI6C100V D e s cription 48- pin SSO P Package
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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